RSA On PSOC4 (Cortex M0)
I am trying to use RSA Signature verification module on Cypress's PSOC4 (32-bit M0S8 based MCU).
One basic question regarding the source code :
How do i configure the bit-size of MCU platform in the source code. I mean how do we specify that platform architecture is 32-bit or 64-bit? What is the default setting?
I basically don't want the code to do 64 bit arithmetic on my MCU and give unexpected results.
Moreover, any pros or cons for implementing RSA on Cortex M0?
The Cypress PSoC4 is based around the Cortex-M0 CPU from ARM, which is a 32bit processor. If you can compile for the PSoC4 you can be sure that only 32bit operations will be performed.
To build for the PSoC4, you can use the GCC compiler that can be found here. The arm-none-eabi variant is suitable for bare metal development such as for the PSoC4.
To answer your final question, mbed TLS offers an implementation of RSA which can be compiled for a Cortex-M0 target, which can be studied to see how it can be done.
Thanks Simon for the response.
I ported RSA implementation of mbedTLS from here:
Tried to run RSA encryption using the in built test functionality of the source code. Looks like PSOC4 (4K RAM) doesn't have enough RAM to run the operation. Used PSOC5 (Based on Cortex M3, 64K RAM). Was able to run the test.
In your last post you mentioned that mbedTLS has RSA implementation for Cortex M0. Is it the same i am using or is there some other repository of the source code for Cortex M0?
Yes, the source code for mbed TLS can be compiled for Cortex M0, as well as many other CPUs and CPU architectures.
We are porting Mbed Os to the PSOC4 BLE module. I want to run a sample application using mbed os on psoc 4 .
I took the Mbed sdk porting guide reference from arm mbed site and I followed the steps of porting and I struck at system clock configuration and system initialization of PSoc 4 module.
Can you please help me out .